entity mux_4_to_1 is
    Port ( I : in std_logic_vector(3 DOWNTO 0);
           SEL : in std_logic_vector(1 downto 0);
           SUM : out STD_LOGIC);
end mux_4_to_1;

architecture Behavioral of mux_4_to_1 is
begin
process(I,SEL) is 
begin
if (SEL(0) <= '0' and SEL(1) <='0') then 
        SUM <= I(0);
    elsif (SEL(0) <= '0' and SEL(1) <='1') then
        SUM <= I(1);
    elsif  (SEL(0) <= '1' and SEL(1) <='0') then 
        SUM <= I(2);
    else 
        SUM <= I(3);
end if;
end process;
end Behavioral;